Modern electronic devices rely on volatile or non-volatile memory to store code or application data processed by application software. Among the different types of non-volatile memory, Flash memory technology has attracted significant attention due to its ability to read and write data in small blocks. There are two architectures commonly used in Flash memory technology, referred to as NOR and NAND architectures, respectively. The NOR architecture, much like a memristor or a phase-change memory, permits fast read random-access that is ideal for code execution and storage. The NAND architecture optimizes the memory cell size and it is suitable for high-density data storage.
The behavior of NAND technology memory bits cannot be fully guaranteed over the lifetime of the memory products. The reliability of each block may vary across the temperature range, the usage conditions, and the lifetime of the products. Due to yield considerations, memories based on the NAND flash architecture are shipped with identified bad blocks. The memory controller is then responsible for the management of these bad blocks over the lifetime of the product. Bad block management, as well as other logic actions such as error code detection and correction, garbage collection, and wear leveling, are the key components of managed-NAND memory controllers. These controllers are systems that include a controller and NAND Flash arrays in the same package and mitigate the NAND reliability issues.
When NAND technology is used to store the boot code, the memory manufacturer guarantees the reliability of the first memory blocks at production time. Typical boot sequences require large memory size which is spread across several memory blocks. System designers usually map the boot sequence at several memory locations to address the lack of reliability of the entire memory array over the lifetime of the electronic device. They rely on error code correction, had block management, and wear leveling techniques to alleviate the shortcomings of NAND technology. These logic blocks however add extra latency to the inherent NAND architecture latency, which can be up to 75 μs for MLC Flash memory. Other reliable system designs use a small external boot memory based on NOR technology to execute the boot code and other sensitive applications. This approach requires an additional chip and interconnections on the device board, which deprives designers from valuable space that could be used for other applications.